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BL8531H afe for ccd/cis signal processor 1 general description the samsung analog front end(afe) for ccd/cis image signal is an integrated analog signal processor for color image signal. the afe converts ccd/cis output signal to digital data. the afe includes three-channel cds(correlated double sampling) circuit, pga(programmable gain amplifier), and 12-bit analog to digital converter with reference generator. a parallel data bus provides a simple interface to 8-bit microcontroller. applications color and b/w scanner digital copiers facsimile general purpose ccd/cis imager fetures 12-bit 6msps a/d converter integrated triple correlated double sampler 3-channel 2 msps color mode analog programmble gain amplifier internal voltage reference wide clamp level controllability for cis sensor no missing code guaranteed microcontroller-compatible control interface operation by single 5v supply cmos low power dissipation key specification resolution: 12-bit conversion rate: 6 mhz(2 mhz*3) supply voltage: 5 v 5% power dissipation: 375 mw(typical)
afe for ccd/cis signal processor bl8531 h 2 functional block diagram red green blue d[11:0] cds pga cds pga cds pga input offset register mux gain register adc ref mpu port ver 2.0 (apr. 2002) no responsibility is assumed by sec for its use nor for any infringements of patents or other rights of third parties that may result from its use. the content of this datasheet is subject to change without any notice.
BL8531H afe for ccd /cis signal processor 3 core pin description name i/o type i/o pad pin description vdda1 ap vdda 5 v analog supply vssa1 ag vssa analog ground vdda2 ap vdda 5 v analog supply(for adc) vssa2 ag vssa analog ground(for adc) vbb ag vbba substarte ground vddd dp vddd 5 v digital supply vssd dg vssd digital ground reft ab piar50_bb reference decoupling refb ab piar50_bb reference decoupling vcom ab piar50_bb analog common voltage bgr ab piar50_bb bandgap refernce voltage r_vin ai piar10_bb analog input; red g_vin ai piar10_bb analog input; green b_vin ai piar10_bb analog input; blue strtln di picc_bb strtln indicates beginning of line cds1_clk di picc_bb cds reset clock pulse input cds2_clk di picc_bb cds data clock pulse input adcclk di picc_bb a/d converter sample clock input csb di picc_bb chip select; active low wrb di picc_bb write strobe; active low rdb di picc_bb read strobe; active low oeb di picc_bb output enable; active low d[11:0]/mpu[7:0] db pia_bb data inputs/outputs ad[2:0] di picc_bb register select mctl1, mctl2 di picc_bb channel select in external mux control ext_mctl di picc_bb external mux control; active low i/o type abbr. ai : analog input di : digital input ao : analog output do : analog output ap : analog power ag : analog ground dp : digital power dg : digital ground ab : analog bidirectional port db : digital bidirectional port
afe for ccd/cis signal processor bl8531 h 4 core pin configuration BL8531H adcclk d[11:0]/mpu[7:0] reft ad[2:0] csb wrb rdb oeb cds2_clk cds1_clk strtln g_vin b_vin r_vin vcom refb vdda1 bgr vssa1 vdda2 vssa2 vddd vssd vbb mctl1,mctl2 ext_mctl absolute maximum ratings charateritics symbol value units supply voltage vdd 6.5 v analog input voltage ain vss to vdd v digital input voltage clk vss to vdd v digital output voltage v oh, vol vss to vdd v reference voltage vrt/vrb vss to vdd v storage temperature range tstg -45 to 150 c operating temperature range topr 0 to 70 c notes: 1. absolute maximum rating specifies the values beyond which the device may be damaged permanently. exposure to absolute maximum rating conditions for extended periods may affect reliability. each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. all voltages are measured with respect to vss unless otherwise specified. 3. 100pf capacitor is discharged through a 1.5k w resistor (human body model)
BL8531H afe for ccd /cis signal processor 5 analog specifications (vdda = 5v, vddd = 5v, adcclk = 6mhz, cds1_clk = 2mhz, cds2_clk = 2mhz, pga gain = 1 unless otherwise noted) characteristics symbol min typ max unit comment resolution 12 bits signal-to-noise & distortion ratio sndr 60 db conversion rate 3-channel with cds 1-channel with cds 6 6 msps msps differential nonlinearity dnl 1 lsb integral nonlinearity inl 2 lsb unipolar offset error 1.0 %fsr gain error 2.0 %fsr anlog input full-scale input input capacitance reference top reference bottom 0.06 8 3.5 1.5 4.0 vp-p pf v v power supply analog voltage digital voltage analog current digital current vdda vddd idda iddd 5 5 65 10 v v ma ma 5v 5% 5v 5% power consumption 375 mw temperature range 0 70 c
afe for ccd/cis signal processor bl8531 h 6 digital specifications (vdda = 5v, vddd = 5v, adcclk = 6mhz, cds1_clk = 2mhz, cds2_clk = 2mhz, cl = 20pf unless otherwise noted) characteristics symbol min typ max unit comment high level input voltage v ih 3.0 v low level input voltage v il 0.8 v high level input current i ih 10 ma low level input current i il 10 ma high level output voltage v oh 4.5 v i oh = 0.5ma low level output voltage v ol 0.5 v i ol = -0.5ma
BL8531H afe for ccd /cis signal processor 7 timing specifications (vdda = 5v, vddd = 5v unless otherwise noted) characteristics symbol min typ max unit 3-channel conversion rate 500 ns 1-channel conversion rate 166 ns cdsclk1 pulse width t c1clk 60 ns cdsclk2 pulse width t c2clk 70 ns cdsclk2b pulse width t c2clkb 70 ns cdsclk1 falling to cdsclk2 rising t c1c2a 5 ns cdsclk2 falling to cdsclk1 rising t c2c1a 5 ns adcclk pulse width t adclk 70 ns cdsclk2 rising to adcclk rising t c2ada 70 ns cdsclk2 falling to adcclk falling t c2adb 5 ns adcclk rising to cds2clk falling t adc2a 5 ns strtln rising, falling setup & hold t s , t h 15 ns adc output delay t addt 20 ns register address setup time t as 15 ns register address hold time t ah 15 ns data hold time t dh 15 ns register chip select setup time t css 15 ns register chip select hold time t csh 15 ns register read pulse width t pwr 50 ns write pulse width t pww 25 ns register read to data valid t dd 40 ns output enable high to tri-state t hz 10 ns tri-state to data valid t dev 15 ns aperture delay t ad 2 ns latency for 1 channel mode 4 adccl k cycles * aperture delay is a timing measurement between the sampling clocks and cds. it is measured from the falling edge of the cds2_clk input to when the input signal is held for data conversion
afe for ccd/cis signal processor bl8531 h 8 timing diagram 3-channel cds mode analog input cds1_clk cds2_clk adcclk strtln t c1c2a t c2c1a t c1clk t c2ada t adc2a t c2clkb t adclk t s t h r0,g0,b0 r1,g1,b1 r2,g2,b2 3-channel sha mode analog input cds2_clk adcclk strtln r0,g0,b0 r1,g1,b1 r2,g2,b2 t c2ada t adc2a t c2clkb t adclk t h t s
BL8531H afe for ccd /cis signal processor 9 1-channel cds mode analog input cds1_clk cds2_clk adcclk t adclk t c2adb t c2clk t c1clk t c2ada t c1c2a t c2c1a
afe for ccd/cis signal processor bl8531 h 10 timing digram 1-channel sha mode analog input cds2_clk adcclk r0,g0,b0 r1,g1,b1 r2,g2,b2 t c2clk t adclk t c2adb t c2ada adc timing adc input adcclk adcout a(n) a(n+1) t addt a(n-2)[11:0] a(n-1)[11:0] a(n)[11:0] a(n-3)[11:0]
BL8531H afe for ccd /cis signal processor 11 write timing ad[2:0] wrb t as t css csb t ah mpu[7:0] t pww t dh t dd oeb t csh
afe for ccd/cis signal processor bl8531 h 12 timing digram read (1) timing ad[2:0] rdb t as t css csb t ah mpu[7:0] t pwr t dh t dd t csh 'read(1)' means microcontroller reads mpu[7:0] csb should keep 'high' to read. read (2) timing adcclk d[11:0] t addt oeb t hz t dev
BL8531H afe for ccd /cis signal processor 13 functional description 1) 3-channel operation with cds this mode enables simultaneous sampling of a triple output ccd. the ccd waveforms are ac coupled to the vinr, ving and vinb pins where they are automatically biased at an appropriate voltage using the on-chip clamp. the internal cdss take two samples of the incoming pixel data; the first samples are taken during the reset time while the second samples are taken during data portion of the input pixels. when strtln is low, the internal circuitry is reset on the next rising edge of adcclk; the multiplexer is switched to red channel. 2) 3-channel sha operation this mode enables simultaneous sampling of a triple output cis or something like that. the cds functions are replaced with the sample and hold amplifiers. the input waveforms are either dc coupled or dc restored to the vinr, ving and vinb pins. the input reference voltage in this mode will be defined by clamp level control register. when strtln is low, the internal circuitry is reset on the next rising edge of adcclk; the multiplexer is switched to red channel. 3) 1-channel operation with cds this mode enables single channel or monochrome sampling. the ccd waveforms are ac coupled to the analog input pin where they are automatically biased at an appropriate voltage using the on-chip clamp. bit2 and bit3 in configuration register select the desired input among red, green and blue. 4) 1-channel sha operation this mode enables single-channel or monochrome sampling. the cds function is replaced with the sample and hold amplifier. the input waveforms are either dc coupled or dc restored to the analog input pin. the input reference voltage in this mode will be defined by clamp level control register. bit2 and bit2 in configuration register select the desired input among red, green and blue.
afe for ccd/cis signal processor bl8531 h 14 main block description 1) programmable gain amplifier the analog programmable gain can accommodate a wide range of input voltage spans. the transfer function of the pga is as follows. h(x) = 1/6*x + 5/6, where the range of x is 0 to 31. thus, the minimum gain value is equal to 5/6, and the maximum gain value is equal to 6. the transfer function has linearity in linear scale. the overall gain is equal to analog gain multiplied by digital gain. so, the multiplier should be required in back end of afe. 0 -2 0 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 2 1 3 4 5 6 pga gain setting gain [db] gain [liner] there is a gain boosting block before 12-bit adc, which can muliply pga's output signal by 1.5 (3.5db) or pass it. this is controled by gain mode of configuration register.
BL8531H afe for ccd /cis signal processor 15 block diagram r_vin red g_vin green b_vin blue cds1_clk cds2_clk adcclk oeb wrb ad[2] d[11:0] /mpu[7:0] csb vdda1 vssa1 vcom vdda2 vssa2 reft refb strtln r_clamp[3:0], r_gain[4:0] r_offset[7:0] g_offset[7:0] b_offset[7:0] r_offset[7:0] 8 r_offset[7:0] g_offset[7:0] b_offset[7:0] r_clamp[3:0]; for only sha mode g_clamp[3:0]; for only sha mode b_clamp[3:0]; for only sha mode b_gain[4:0] r_gain[4:0] g_gain[4:0] rdb ad[1] ad[0] 8 bgr vddd vssd vbb mctl2 mctl1 ext_mctl gain mode cds clamp pga cds clamp pga cds clamp pga mux & g1.5 adc ref configuration register input offset register (r,g,b) gain & clamp level register (r,g,b) g_clamp[3:0], g_gain[4:0] b_clamp[3:0], b_gain[4:0] mpu port 12 12
afe for ccd/cis signal processor bl8531 h 16 table: mpu port map format a2 a1 a0 register 0 0 0 configuration register 0 0 1 input offset register 0 1 0 pga gain control register 0 1 1 cis clamp control register 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved 2) register overview the mpu port map is accessed through pins a0, a1 and a2. see mpu port map format.(previous page) configuration register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clamp mode select1 clamp mode select0 pga gain mode external reference color1 color0 single channel cds enable single channel color pointer bit3 bit2 color 0 0 red 0 1 green 1 0 blue 1 1 reserved clamp mode selection bit7 bit6 clamp mode 0 0 line clamp 0 1 pixel clamp 1 0 no clamp 1 1 reserved
BL8531H afe for ccd /cis signal processor 17 input offset register msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pga gain control register msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved pga4 pga3 pga2 pga1 pga0 cis clamp control register msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved ccc3 ccc2 ccc1 ccc0 * cccn: cis clamp control n multiplexer control mode ext_mctl = "low" mctl2 mctl1 color 0 0 red 0 1 green 1 0 blue 1 1 reserved
afe for ccd/cis signal processor bl8531 h 18 overrall transfer function the overall transfer function can be calculated as follows. if gain mode = 0, adc out = [( vin+input_offset)* pga_gain]/(2*ref)*4096, if gain mode = 1, adc out = [( vin+input_offset)* pga_gain * 1.5]/(2*ref)*4096, where ref is equal to (reft-refb) and input _offset means the dac value of the input offset register. the analog offset range of the input offset register is varied between 150mv and -150 mv. the 8-bit data format for the input offset register is straight binary coding. thus, an all 'zeros' data word corresponds to -150 mv. an all 'ones' data word corresponds to 150 mv. to maximize the dynamic range of the adc input, it is necessary to program the input offset register code to move the adc code corresponding to the black level towards 'zero'. in case of processing cis signal, 4-bit of the gain & clamp control register are allocated to control cis clamp level. like the input offset register, the 4-bit data format is straight binary coding. an all 'zeros' data word corresponds to 0.1 v and an all 'ones' data word corresponds to 1.5 v. input coupling capacitor because of the dc offset present at the output of ccd, some kind of dc restoration is required. in case of cds enable mode, to simplify input level shifting, a dc decoupling capacitor is used in conjuction with the internal input circuitry. the capacitor charging or discharging depends on the clamping time, the analog input resistance of the afe and the output resistance of the circuit driving the coupling capacitor. the clamping time is typically ( n*t), where n is the number of periods cdsclk1 is asserted and t is the period of assertion. cdsclk2 should not be asserted during clamping time. and, strtln must be low in line clamp mode for clamping operation. the analog input resistance of the afe is equal to 1 k w . the recommended input coupling capacitor is more than 0.01uf. thus, to extend the clamping time, the time a transport motor moves the scanner carriage can be available, for example.
BL8531H afe for ccd /cis signal processor 19 yes no yes no yes no power-on initialization calibration write to configuration register set cds or sha operation set 3 or 1 channel mode set color pointer set clamp mode write to pga gain register set to gain of one(00001) write to input offset register set to 0mv(10000000) set another color decide clamp level for sha mode (refer to next page) set pga gain (input offset = 0mv) scan dark line compute pixel offsets set input offset set odd/even offset in back end set another color set gain/offset bus size in back end set external pixel offset in back end scan white line compute pixel gains in back end adjust pga gain
afe for ccd/cis signal processor bl8531 h 20 clamp level decision for each input * assume that pga gain = 1 * this flow chart is not fixed, but recommended. user can modify this algorithm. adc output > 0 yes no no no yes yes yes yes no no [min(adc output) = minimum value of all pixels] [repeatedly, scan clamp level. average adc output] [(100mv)/(4v) * 4096 - 1 = 102] write cis clamp control register set to (111) scan clamp level input scan dark line min(adc output) > 102 min(adc output) > 0 decrease cis clamp control register by 1 min(adc output) > 204 increase cis clamp control register by 1 increase cis clamp control register by 1 decrease cis clamp control register by 1 scan dark line min(adc output) > 102 increase cis clamp control register by 1 go to calibration
BL8531H afe for ccd /cis signal processor 21 core evaluation guide BL8531H adcclk d[11:0] reft ad[2:0] csb wrb rdb oeb cds2_clk cds1_clk strtln g_vin b_vin r_vin vcom refb bgr vdda1 vdda2 vssa1 vssa2 vddd vssd vbb mctl1,mctl2 ext_mctl 0.1u 0.1u 0.1u 0.1u timing generator mpu interface dsp asic mux mux externally forced digital input/output
afe for ccd/cis signal processor bl8531 h 22 package configuration the digital pins should be well decoupled to the analog ground plane. refb csb d[8] d[9] d[10] d[11] ext_mctl mctl1 mctl2 ad[0] ad[1] ad[2] vbb vssa1 vdda1 b_vin g_vin r_vin speedup BL8531H afe85 48 qfp ibias nc stby itest nc vdda2 vssa2 vsso vddo d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] reft vcom bgr vssd vddd strtln cds1_clk cds2_clk adcclk oeb wrb rdb 0.1u 50 0.01u 0.01u 50 0.01u 50 10u 0.1u 0.1u 10u :analog ground :digital ground 50 50 50 10u 0.1u 0.1u 0.1u 0.1u
BL8531H afe for ccd /cis signal processor 23 package pin description pin no. pin name i/o type description 1 nc - not connected 2 vdda2 ap analog power for a/d converter 3 vssa2 ag analog ground for a/d converter 4 vsso dg output buffer ground 5 vddo dp output buffer power 6 d[0]/mpu[0] db digital output lsb/register input lsb 7 d[1]/mpu[1] db digital output/register input 8 d[2]/mpu[2] db digital output/register input 9 d[3]/mpu[3] db digital output/register input 10 d[4]/mpu[4] db digital output/register input 11 d[5]/mpu[5] db digital output/register input 12 d[6]/mpu[6] db digital output/register input 13 d[7]/mpu[7] db digital output/register input msb 14 d[8] db digital output 15 d[9] db digital output 16 d[10] db digital output 17 d[11] db digital output msb 18 mctl1 di color pointer for mux control 19 ext_mux di mux control mode selection low : by mctl1, mctl2 high : by configuration register 20 mctl2 di color pointer for mux control 21 ad[0] di register selection pin 22 ad[1] di register selection pin 23 ad[2] di register selection pin 24 csb di chip selection (active low)
afe for ccd/cis signal processor bl8531 h 24 package pin description (continued) pin no. pin name i/o type description 25 rdb di read strobe (active low) 26 wrb di write strobe (active low) 27 oeb di output enable (active low) 28 adcclk di a/d converter clock input 29 cds2_clk di cds data clock input 30 cds1_clk di cds reset clock input 31 strtln di start line (active low) 32 vddd dp digital power 33 vssd dg digital ground 34 bgr ab bandgap reference voltage 35 vcom ab reference middle voltage 36 reft ab reference top voltage 37 refb ab reference bottom voltage 38 r_vin ai red analog input 39 g_vin ai green analog input 40 b_vin ai blue analog input 41 ibias ab analog test pin (floating) 42 vdda1 ap analog power 43 vssa1 ag analog ground 44 vbb ag analog ground 45 nc - not connected 46 speedup di test pin ( set to low) 47 stby di stand by (power down) low = normal high = power save 48 itest ab analog test pin (floating)
BL8531H afe for ccd /cis signal processor 25 user guide configuration it is necessary that output signal of analog front end be shading-compensated by back end logic block including subtracter and multiplier. shading-compensation block ccd/cis afe subtracter multiplier controller memory output bus controls csb 0 0 0 0 1 1 wrb 0 1 1 1 x x rdb 1 x 0 x x x oeb 1 0 x 1 0 1 dout mpu input x mpu output z adc output z x: don't care x: unknown (not recommended) z: high impedance
afe for ccd/cis signal processor bl8531 h 26 phantom cell information ? pins of the core can be assigned externally (package pins) or internally (internal ports) depending on design methods. the term "external" implies that the pins should be assigned externally like power pins. the term "external/internal" implies that the applications of these pins depend on the user. vdda2 vssa2 vddo vsso do[0] do[1] do[2] do[3] do[4] do[5] do[6] do[7] do[8] do[9] do[10] do[11] ad[0] ad[1] ad[2] csb rdb wrb oeb cds2_clk cds1_clk vssd vssd vddd vddd adcclk strtln itest stby speedup mctl2 mctl1 ext_mctl bgr ibias vdda1 vssa1 vbb refb reft vcom vdda1 b min vssa1 vbb g min r min BL8531H 12-bit 6 msps afe for image processor
BL8531H afe for ccd /cis signal processor 27 pin name pin usage pin layout guide vdda1 external - maintain the large width of lines as far as the pads. vssa1 external - place the port positions to minimize the length of power lines. vdda2 external - do not merge the analog powers with other power from other vssa2 external blocks. vddd external - use good power and ground source on board. vssd external vddo external vsso external vbb external r_vin external/internal - do not overlap with digital lines. g_vin external/internal - maintain the shortest path to pads. b_vin external/internal adcclk external/internal - separate from all other analog signals cds1_clk external/internal cds2_clk external/internal reft external/internal - maintain the larger width and the shorter length as far as the pads. refb external/internal - separate from all other digital lines. vcom external/internal bgr external/internal ibias external/internal - test pins itest external/internal - speedup = set to "low" stby external/internal speedup external/internal strtln external/internal - separated from the analog clean signals if possible. ext_mctl external/internal - do not exceed the length by 1,000um. mctl1,2 external/internal oeb external/internal wrb external/internal rdb external/internal csb external/internal ad[2:0] external/internal d[11:0] external/internal
afe for ccd/cis signal processor bl8531 h 28 feedback request it should be quite helpful to our afe core development if you specify your system requirements on afe in the following characteristic checking table and fill out the additional questions. we appreciate your interest in our products. thank you very much. characteristics symbol min typ max unit comment resolution bits signal-to-noise & distortion ratio sndr db conversion rate 3-channel with cds 1-channel with cds msps msps differential nonlinearity dnl lsb integral nonlinearity inl lsb unipolar offset error %fsr gain error %fsr anlog input full-scale input vp-p power supply analog voltage digital voltage vdda vddd v v power consumption mw temperature range c ? what do you want to choose as power supply voltages? for example, the analog vdd needs to be 5v. the digital vdd can be 3.3v/5v. ? which modes of afe do you use for overall system ? (refer to page 9) for example: 3channel operation with cds / 3channel shi(cis) operation 1channel operation with cds / 1channel shi(cis) operation ? would you define the gain range and input offset range ? ? could you explain external/internal pin configurations as required? ? should the bus interface be compatible with ttl ? ? when strtln is low, the internal circuit is reset on the rising edge of adcclk. which channel is multiplexer switched to on the next rising edge of adcclk, after strtln goes high? ? if possible, present other requirements below.
BL8531H afe for ccd /cis signal processor 29 history card version date modified items comments ver 1.0 98.11 original version published (preliminary) ver 1.1 99.1 release the formal data sheet ver 2.0 02.4.16 change the data sheet format, phantom information added
afe for ccd/cis signal processor bl8531 h 30 notes

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